1. Field of the Invention
The present invention relates to a fabrication method used for semiconductor devices, and more specifically to an improved process for metal oxide semiconductor field effect transistor, (MOSFET), structures, via use of a buried contact feature.
2. Description of Prior Art
The ability of the semiconductor industry to continually reduce the cost of semiconductor chips, while still maintaining, or improving device performance, is directly related to the ability of the industry to fabricate smaller and denser chips. For example micro-miniaturization has allowed specific semiconductor elements to be packed more densely on a chip, thus decreasing specific resistances, resulting in performance enhancements. In addition the trend to micro-miniaturization has resulted in smaller semiconductor images, allowing more circuits per chip to be realized, thus resulting in cost reductions. The major advances in the semiconductor industry, responsible for micro-miniaturazation, has been the breakthroughs in the photolithographic and reactive ion etching, (RIE), disciplines. More sophisticated exposure cameras, as well as the development of more sensitive photoresist materials, have resulted in sub-micron images, in photoresist, to be routinely achieved. The advances in RIE tools, as well as the development of specific RIE ambients, have allowed the successful transfer of sub-micron images in photoresist, to underlying materials, used in the semiconductor fabrication process.
In addition to the advances in specific semiconductor disciplines, the development of specific process sequences, has also contributed to the increases in chip density. For example the invention of the sidewall technology, used extensively in complimentary metal oxide semiconductor, (CMOS), devices, has had a positive impact on device density. Another process sequence, used to decrease chip size, has been the buried contact process. For example in CMOS devices, the contact to source and drain regions, if made in the active device region, would require large silicon areas, thus negatively impacting density, Therefore processes and structures were developed, in which contact to these source and drain regions, could be made through a polysilicon structure. Therefore access to the source and drain region can be made by contacting the polysilicon layer, in a non-critical device area. The polysilicon layer in turn, contacts the the source and drain regions, via a process known as the buried contact scheme. In U.S. Pat. No. 4,341,009, Bartholomew, et al, describe a specific buried contact process, used for the fabrication of MOSFETs. However that process is complex, requiring a significant increase in process steps, and thus compromising the density benefits, with cost increases. The invention now described, will show a simpler, more cost effective process for achieving the buried contact scheme.